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Title: 高介電空間層無源/汲極接面電晶體之特性模擬研究
Other Titles: Effect of Different High-κ Spacer on Characteristic of Junctionless Field Effect Transistor (JL-FET)
Authors: 陳, 昱志; 張, 聖偟
Keywords: 空間層介電常數
Dielectric constant
High-κ spacer
High-κ material Junctionless
Sidewall spacer
Issue Date: 6-3-2017
Abstract: 本專題研究我們利用高介電係數閘極側壁空間層(Spacer)進行短通道無接面電晶體(JL-FET)之特性改善研究,透過理論分析與元件模擬預測結果。藉由使用半導體元件模擬軟體Synopsys TCAD Sentaurus進行3D鰭式元件結構LG=80 nm、W=40 nm與通道厚度Tsi=26 nm,進行元件最佳化模擬,並且針對不同空間層材料例如: HfO2(κ=25)、Si3N4(κ=7.5)、SiO2(κ=3.9)等對無接面電晶體造成之I-V特性曲線、DIBL效應與元件漏電流影響作一探討。模擬結果分析,側壁空間層之介電常數越高越能有效降低元件漏電流,並提升輸出電流Ion,改善短通道元件之元件開關比(Ion/Ioff)與 DIBL效應,故使用HfO2空間層能對JL-FET帶來最佳的電性。
In this study, we investigate in the high dielectric constant spacer at device gate sidewall to improve the characteristics of short channel junctionless transistor (JL-FET). With theoretical analysis and device simulation results; therefore, we measure the actual product to verify the expected results. Firstly, we simulated the device structure of the 3D FinFET structure with LG = 80 nm, W = 40 nm and channel thickness TSi = 26 nm achieve the optimal results, using a semiconductor device simulation software of the Synopsys Sentaurus TCAD. And also discussed the effects of JL-FET with different spacer materials, such as HfO2 (κ = 25), Si3N4 (κ = 7.5) and SiO2 (κ = 3.9) on the I-V characteristic curve, DIBL effect and leakage current. The simulation results show that the higher dielectric constant of the spacer, the more effectively reduce the off-state leakage current, increase the output current Ion, improve the on/off current ratio and DIBL effect for the short channel JL-FET. Therefore, JL-FET with HfO2 spacer will have the best device performance.
???metadata.dc.description.instructor???: 林, 成利
???metadata.dc.description.course???: 專題研究(二)
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